Current demands for high density and performance associated with ultra large scale integration require submicron features, increased transistor and circuit speeds and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
A conventional in-process monitoring technique employs a two phase “inspection and review” procedure. During the first phase the surface of the wafer is inspected at high-speed and relatively low-resolution. The purpose of the first phase is to produce a defect map showing suspected locations on the wafer having a high probability of a defect. During the second phase the suspected locations are more thoroughly analyzed. Both phases may be implemented by the same device, but this is not necessary.
The two phase inspection tool may have a single detector or multiple detectors. Multiple detector two phase inspection devices are described, by way of example, in U.S. Pat. Nos. 5,699,447, 5,982,921, and 6,178,257.
U.S. patent application Ser. No. 13/495,824 entitled “Apparatus and Method for Defect Detection Including Patch to Patch Comparison” discloses apparatus and method for defect detection including patch to patch comparison.
Defect detection systems for detecting defects in patterned microscopic objects, include for example the following:
United States Patent Application No. USSN 20080106740, entitled “Dual stage defect region identification and defect detection method and apparatus”;
United States Patent Application No. USSN 20090148033, “Optical Inspection Apparatus For Substrate Defect Detection”;
U.S. Pat. No. 6,064,484, entitled “Pattern inspection method and system”;
U.S. Pat. No. 6,829,047, entitled “Defect detection system”; U.S. Pat. No. 7,630,535 entitled “Die-to-die photomask defect detection using region data to modify inspection thresholds”;
U.S. Pat. No. 7,801,353, entitled “Method for defect detection using computer aided design data”.
State of the art Applied Materials inspection systems are described and claimed in U.S. Pat. Nos. 5,982,921; 6,178,257; 6,952,491; 7,796,807; 7,499,583; 5,699,447; 6,829,381; 7,379,580; 7,410,737; 7,054,480; 6,862,491.
FIG. 1 is an illustration of a wafer 10 such as ones which may be used in the fabrication of integrated circuits and other microdevices. While the term wafer may be used to refer only to the substrate material on which the integrated circuit is fabricated (e.g. a thin slice of semiconductor material, such as a silicon crystal), this term may also be used to refer to the entire construction, including the electronic circuit fabricated on the wafer.
The wafer 10 is divided into multiple dies 11 which are illustrated in a widely implemented rectangular form. Like the term ‘wafer’, the term ‘die’ may also be used either for small blocks of semiconducting material, on which a given functional circuit is fabricated, or for such a block including the fabricated electric circuit. Usually, wafer 10 may be cut (“diced”) into its multiple dies 11, wherein all of the dies of the wafer contain a copy of the same electronic circuit. While not necessarily so, each of the dies 11 is independently functional.
A single die may include a large amount of patterns that well exceed millions of patterns per die. A semiconductor die usually includes a plurality of layers. A pattern, such as local pattern 24 may be a part of a metal interconnection line, a trench, a via, a conductive gate, etc. Different areas on each die may be put to different uses; such areas may be for example background areas (that are ideally very smooth), memory areas (that include a large number of repetitive patterns) and logic areas (that usually do not include large quantities of adjacent repetitive patterns).
There exists a need for improved and more robust techniques for detecting defects in a substrate, and especially semiconductor substrate defects.